1. Technical Field
This invention relates generally to analog signal comparators, and more particularly, to an apparatus and method for combining existing analog comparators to produce a single event upset immune comparator for use in the outer space environment.
2. History of Related Art
Analog voltage comparators are used in almost every area of electronic circuitry, such as power supplies, data transmission and reception, and data acquisition. Typically, the comparator provides a logic-level signal at its output, depending on the relative voltage values present at each one of two inputs. The output voltage level is thus determined by which one of the inputs has a higher voltage level. For example, if the comparator has an input labeled "plus," and an input labeled "minus," then the output will go to a low logic-level if the minus input voltage value is higher than the voltage value present at the plus input. However, if the plus input voltage value is higher than that present at the minus input, the output will be driven to a high logic-level.
A Single Event Upset (SEU) typically refers to the interrupted function of a digital electronic circuit, usually occurring at the single-bit level, when a particle of ionizing radiation impacts upon the circuit and changes the logic-value of its output. The exact effect of any SEU depends on the particular device involved, and its relation to other components in a particular circuit. The generalized effect for a logic-dependent circuit is the changing of an output value from its normally expected level to the opposite (e.g., "1" to "0" or "0" to "1"). Such changes, induced by ionizing radiation, generally result in unexpected and undesirable circuit performance.
Due to the shielding effects of the earth environment, SEUs due to ionizing radiation are not normally considered as part of electronic circuit design. However, in the outer space environment, where electronic components may perform functions of a more critical nature (e.g., failure may result in the loss of life or a very expensive spacecraft), the SEU becomes part of many electronic design decisions.
SEU immune circuitry has been developed for various digital logic families. However, such circuitry (e.g. silicon-on-sapphire) may be prohibitively expensive or very difficult to procure in a timely fashion due to limited production runs. Other logic families, such as Complementary Metal Oxide Semiconductor (CMOS) logic, are SEU immune, but may not have the desired current-drive ability. Further, many digital logic SEU immune approaches have been advanced, but analog components which are SEU immune have not received the same attention by manufacturers.
Therefore, what is needed is a design approach to provide SEU immune comparators for use in the outer space environment which is relatively independent of the logic family employed, and does not require a prohibitively expensive technology for manufacture. Further, since conventional comparators are beset by the problem of offset voltage and currents at the inputs, it would be desirable to provide a SEU immune comparator design which accommodates such offset voltage and currents to produce a reliable comparator output even when the input voltages are fairly close to each other in value.
Further, since individual comparators are typically manufactured as dual, quad, or larger groupings of identical units in a single package, it would be desirable to provide a SEU immune comparator which takes advantage of multiple unit packaging and minimizes the use of non-identical components for enhanced reliability. In addition, since the power used and volume occupied by electronic circuitry is to be minimized in the outer space environment, it is desirable to provide a SEU comparator deign which makes use of the least possible number of electronic components so as to provide an attractive alternative to other methods which result in greater power consumption or larger amounts of circuit real estate consumed.